1. Field of the Invention
The present invention relates to semiconductor devices having trench-gate transistors. The present invention also relates to manufacturing methods of semiconductor devices. The present invention further relates to data processing systems including semiconductor devices.
The present application claims priority on Japanese Patent Application No. 2008-55104, the content of which is incorporated herein by reference.
2. Description of Related Art
Recently, semiconductor devices have been developed to have fine structures for transistors and to therefore suffer from deterioration of sub-threshold characteristics (referred to as “S-factor”) such as reductions of threshold voltages due to short-channel effects. So-called fin-shaped field-effect transistors (referred to as “Fin-FET”) using SOI (Silicon On Insulator) substrates have become popular among semiconductor manufacturers as high-performance transistors which do not cause S-factor deterioration. Various types of Fin-FET have been developed and disclosed in various documents such as Patent Document 1 and Patent Document 2.                Patent Document 1: Japanese Unexamined Patent Application Publication No. 2007-158269        Patent Document 2: Japanese Unexamined Patent Application Publication No. 2007-258660        
Both of the above documents teach transistors having fin-shaped SOI structures which are formed inside trenches in active regions for use in channels.
SOI substrates are expensive in comparison with generally-used substrates composed of monocrystal silicon; hence, it is difficult to use SOI substrates for versatile products such as dynamic random-access memory (DRAM) produced at low cost.
The present inventor has recognized that the Fin-FET disclosed in Patent Documents 1 and 2 are depletion-type transistors having thin silicon layers serving as channel regions, which have difficulty in adjusting threshold voltages by controlling impurity densities of channel regions in transistors. For this reason, it is necessary to develop semiconductor devices including transistors such as Fin-FET having thin silicon layers serving as channel regions, which can be easily controlled in threshold voltages.